Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits
US7141485B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2003 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jun 13, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for reducing sidewall capacitance by 25% or more in an STI structure is described. A conformal barrier layer is deposited on sloped sidewalls in a shallow trench within a substrate. The trench is filled with a low k dielectric material which is planarized and etched back. Next a barrier cap layer is deposited that is different than the underlying low k dielectric layer. In one embodiment, the barrier cap layer is a SiCOH material that is modified for enhanced CMP performance that yields fewer surface scratches and defects. A nitride etch stop layer and a pad oxide are removed above an active area on the substrate to afford the final STI structure. Optionally, the barrier cap layer is omitted and the low k dielectric layer extends slightly above the substrate level. Total parasitic capacitance in the resulting MOS device is reduced by 15% or more.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.