Cheng Hsiao
8Patents
2h-index
18Co-inventors
44Inventor score
Filing activity: Jan 15, 2003 → Dec 19, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7141485B2 | Shallow trench isolation structure with low sidewall capacitance for high speed integrated circuits | Electricity | 5 | Expired |
| US10521538B2 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Physics | 3 | Active |
| US10019545B2 | Simulation scheme including self heating effect | Physics | 2 | Active |
| US7421383B2 | Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof | Physics | 2 | Expired |
| US9904743B2 | Method for analyzing interconnect process variation | Physics | 2 | Active |
| US10216879B1 | Method for establishing aging model of device and analyzing aging state of device with aging model | Electricity | 1 | Active |
| US10860769B2 | Method and system for integrated circuit design with on-chip variation and spatial correlation | Physics | 0 | Active |
| US9558314B2 | Method of designing circuit layout and system for implementing the same | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.