Buried word line memory integrated circuit system
US7141838B1 · kind B1 · utility
3Cited by
4References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 27, 2005 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jan 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
Abstract
An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.