Transistors having a recessed channel region
US7141851B2 · kind B2 · utility
2Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Aug 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/018
Abstract
A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.