Semiconductor device
US7141879B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2001 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | May 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15174
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is described an improved semiconductor device of chip-scale package (CSP) comprising posts provided on respective electrode pads of a semiconductor chip, and solder balls which are provided on the respective posts as external terminals after the semiconductor chip has been encapsulated with resin while the posts are held in a projecting manner. The semiconductor device prevents occurrence of cracks, which would otherwise be caused by stress which is induced by a difference in coefficient of linear expansion between the semiconductor chip and the sealing resin and is imposed on the posts. In order to alleviate the stress imposed on the posts, a stress-absorbing layer formed from a metal layer having a low Young's modulus, such as gold (Au) or palladium (Pd), is interposed in the middle of each of the posts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.