Metal line stacking structure in semiconductor device and formation method thereof
US7141880B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 2003 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jul 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76838
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method for forming a metal line stacking structure according to a preferred embodiment of the present invention comprises: sequentially forming a first barrier metal and a first metal layer on a lower dielectric layer that is disposed over a semiconductor substrate, and performing a plasma treatment; forming a second barrier metal on the plasma-treated first metal layer; selectively etching the second barrier metal, the first metal layer, and the first barrier metal to form a metal line layer including the second barrier metal, the first metal layer, and the first barrier metal, which respectively have a predetermined width; and sintering the metal line layer to raise a reaction between the first metal layer and the second barrier metal, thereby generating a metal compound layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.