Tag array access reduction in a cache memory
US7143243B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 29, 2003 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Feb 18, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory is disclosed with reduced tag array searches for sequential memory accesses. The cache memory has components such as at least one tag array, at least one data array associated with the tag array, a tag read control logic module for controlling a tag array search, a comparator associated with the tag array, and a storage module for storing a match result of the comparator while processing a first memory access request that accesses a first data address in a first cacheline of the data array. The stored match result is used for a second memory access request that intends to access a second data address sequential to the first data address, thereby avoiding searching the tag array for the second memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.