Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system
US7143257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2003 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jun 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of reading a plurality of words during a clock latency period and shifting them out synchronously after the latency period is facilitated by a two tier column decoder. The two-tier column decoder has two decoders. A first-tier decoder decodes a first group of words to be read during the latency period, and a second-tier decoder decodes subsequent words to be shifted out synchronously during a burst period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.