Partitioning prefetch registers to prevent at least in part inconsistent prefetch information from being stored in a prefetch register of a multithreading processor
US7143267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2003 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Sep 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and multithreaded processor for dynamically reallocating prefetch registers upon the processor switching modes of operation. An execution unit may be coupled to a prefetch engine where the execution unit may be configured to receive prefetch instructions regarding prefetching data. The prefetch engine may comprise a plurality of prefetch registers. The execution unit may further be configured to load the plurality of prefetch registers with information regarding prefetching data obtained from the prefetch instructions. In a single thread mode of operation, the plurality of prefetch registers are allocated to be accessed by either a first or a second thread. In a multithread mode of operation, the plurality of prefetch registers are allocated to be accessed among the first and second threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.