DSP design system level power estimation
US7143368B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Feb 15, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power consumption estimation is performed at the system level in a design process, thus allowing early evaluation of feasibility and other considerations relating to logic/DSP design and hardware implementation of a proposed electronic design. Evaluation of the system level power consumption estimate(s) permits adjustment of a system level representation of the proposed electronic design, prior to investment of substantial resources in the electronic design. Other estimates, including other power consumption estimates, may be performed to adjust the proposed electronic design as well. Such estimates may be made in response to gate level power consumption estimates and/or hardware level power consumption estimates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.