Patent · US Expired

Method and apparatus for design verification with equivalency check

US7143376B1 · kind B1 · utility

19Cited by
10References
31Claims
0Family size

Assignee

Inventor

Key dates

Filing dateMar 2, 2004
Grant dateNov 28, 2006
Priority date—
Expiry dateFeb 3, 2025

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/31704
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

Method and apparatus for design verification with equivalency checking is described. More particularly, an integrated circuit design for a device having programmable logic is obtained, and a test case design having one or more test patterns is obtained to test the integrated circuit design. Memory states for the test patterns are obtained and applied to configure at least a programmable logic portion of the integrated circuit design with at least one test pattern to provide a configured design. Equivalency checking with the at least one test pattern and the configured design may be done to determine if the configured design is functionally equivalent to the at least one test pattern.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.