Systems and methods for generating node level bypass capacitor models
US7143389B2 · kind B2 · utility
1Cited by
10References
26Claims
0Family size
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Key dates
| Filing date | Jul 28, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Mar 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods associated with generating node level bypass capacitor models are disclosed. One embodiment of a system may comprise a plurality of bypass capacitor circuit models associated with respective bypass capacitors and a node level model generator. The node level model generator may associate bypass capacitor information for a plurality of bypass capacitors from a data base associated with a multi-layer structure design with respective bypass capacitor circuit models to provide a node level capacitor model for the plurality of bypass capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.