Charge-trapping memory device

US7144776B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ricardo P. Mikalo · Stadtroda, DE
• Erwin Schroer · Catania, IT
• Gunther Wein · Nittendorf, DE
• Jens-Uwe Sachse · Dresden, DE
• Mark Isler · Lebanon, US
• Jan-Malte Schley · Dresden, DE
• Christoph Kleint · Dresden, DE

Key dates

• Filing date: May 31, 2005
• Grant date: Dec 5, 2006
• Expiry date: May 31, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0413

Abstract

An oxidized region is arranged between a substrate of semiconductor material and a nitride liner, which covers wordline stacks of a memory cell array and intermediate areas of the substrate, and is provided to separate the nitride liner both from the substrate and from a memory layer sequence of dielectric materials that is provided for charge-trapping. The nitride liner is used as an etching stop layer in the formation of sidewall spacers used in a peripheral area to produce source/drain junctions of transistors of the addressing circuitry.