Semiconductor integrated circuit device and process for manufacturing the same
US7145193B2 · kind B2 · utility
0Cited by
18References
4Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 29, 2002 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Oct 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a peripheral circuit region of a DRAM, two connection holes, for connecting a first layer line and a second layer line electrically are opened separately in two processes. After forming the connection holes, plugs are formed in the respective connection holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.