Seal ring for mixed circuitry semiconductor devices
US7145211B2 · kind B2 · utility
16Cited by
6References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2004 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Sep 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Appropriate predetermined sections of such a mixed use chip are isolated from the substrate through a non-ohmic contact with the substrate without compromising reliability of the chip's isolation from scribe region contamination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.