Clock signal-distribution network for an integrated circuit
US7145362B1 · kind B1 · utility
21Cited by
3References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2004 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Feb 5, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus for signal distribution, and more particularly to a clock-distribution network in an integrated circuit, is described. A programmable logic device 300 includes an input buffer (814, 824) and an input signal distribution buffer (369) coupled to the input buffer (814, 824). The input signal distribution buffer (369) is configured to distribute a clock signal (902) within an input/output block clock region (304A, 304B). Signal lines (371UD) extend to at least one other input signal distribution buffer (369).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.