Single cycle refresh of multi-port dynamic random access memory (DRAM)
US7145829B1 · kind B1 · utility
29Cited by
11References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 16, 2005 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Jun 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored data from a refresh buffer into a row in the memory array and then reads data from one row of the memory array into the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.