Hiding refresh in 1T-SRAM architecture
US7146454B1 · kind B1 · utility
24Cited by
11References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2002 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Feb 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/3042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and device for handling the refresh requirements of a DRAM or 1-Transistor memory array such that the memory array is fully compatible with an SRAM cache under all internal and external access conditions. This includes full compatibility when sequential operations alternate between memory cells in same row and column locations within different memory banks. The device includes bi-directional buses to allow read and write operations to occur between memory banks and cache over the same bus. The refresh operations can be carried out without interference with external accesses under any conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.