Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid

US7146596B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Thomas R. Bednar · Pewaukee, US
• Timothy W. Budell · Colchester, US
• Patrick H. Buffet · South Burlington, US
• Alain Caron · South Burlington, US
• James V. Crain, Jr. · Colchester, US
• Douglas W. Kemerer · South Burlington, US
• Donald S. Kent · South Burlington, US
• Esmaeil Rahmati · South Burlington, US

Key dates

• Filing date: Aug 29, 2003
• Grant date: Dec 5, 2006
• Expiry date: Aug 2, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit chip having a contact layer that includes a plurality of Vdd, Vddx, ground and I/O contacts arranged in a generally radial pattern having diagonal and major axis symmetry and generally defining four quadrants. A multilayer X-Y power grid is located beneath the contact layer. A wiring layer is interposed between the contact layer and power grid to provide a well-behaved electrical transition between the generally radial Vdd, Vddx and ground contacts and the rectangular X-Y power grid. The interposed wiring layer includes concentric square rings of Vdd, Vddx and ground wires located alternatingly with one another. The Vddx wires are discontinuous between adjacent quadrants so that the magnitude of Vddx may be different in each quadrant of the chip if desired.