IC chip package structure and underfill process
US7148560B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2005 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Jan 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A novel integrated circuit (IC) chip package structure and underfill process which reduces stress applied to corners of a flip chip in an IC package structure during the application of an adhesive material between the flip chip and a carrier substrate is disclosed. The process includes providing a dam structure on a carrier substrate; attaching solder bumps of an inverted flip chip to the carrier substrate; injecting an adhesive material between the flip chip and the carrier substrate at multiple injection points located along adjacent edges of the flip chip; and injecting a sealant material around the adhesive material. During application of the adhesive material and the sealant material to the IC package structure in the underfill process, the dam structure reduces stress applied to the corners of the flip chip. This prevents or at least reduces de-lamination of dielectric layers on the flip chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.