Stacked microelectronic assemblies

US7149095B2 · kind B2 · utility

Assignee

• TESSERA LLC · US

Inventors

• Michael Warner · San Jose, US
• Philip Damberg · Cupertino, US
• John Riley · Dallas, US
• David Gibson · Palo Alto, US
• Young Gon Kim · Daejeon, KR
• Belgacem Haba · Cupertino, US
• Vernon Solberg · Saratoga, US

Key dates

• Filing date: Oct 28, 2002
• Grant date: Dec 12, 2006
• Expiry date: May 27, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A stacked microelectronic assembly includes a plurality of microelectronic subassemblies. Each subassembly includes a substrate having at least one site, a plurality of first contacts and a plurality of second contacts. Each subassembly also has at least one microelectronic element assembled to the at least one attachment site and electrically connected to at least some of the first and second contacts. The substrate is folded so that the first contacts are accessible at a bottom of a subassembly and the second contacts are accessible at a top of a subassembly. The plurality of subassemblies are stacked one on top of another in a generally vertical configuration. The substrate of at least one of the subassemblies has a plurality of attachment sites and a plurality of microelectronic elements assembled to the attachment sites. The substrate is folded so that at least some of the plurality of microelectronic elements are disposed alongside one another.