Memory device with column select being variably delayed
US7149134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2005 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Oct 26, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder (18) is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.