Virtual reassembly system and method of operation thereof
US7149211B2 · kind B2 · utility
69Cited by
12References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2004 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Nov 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5679
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.