Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor
US7149880B2 · kind B2 · utility
10Cited by
2References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Apr 18, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for a simultaneous multithreaded processor that reduces the number of hardware components necessary as well as the complexity of design over current systems is disclosed. As opposed to requiring individual storage elements for saving instruction pointer information for each re-steer logic component within a processor pipeline, the present invention allows for instruction pointer information of an inactive thread to be stored in a single, ‘inactive thread’ storage element until the thread becomes active again.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.