Method and apparatus for improving dispersal performance in a processor through the use of no-op ports
US7149881B2 · kind B2 · utility
2Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2004 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Apr 22, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for improving dispersal performance of instruction threads is described. In one embodiment, the dispersal logic determines whether the instructions supplied to it include any NOP instructions. When a NOP instruction is detected, the dispersal logic places the NOP into a no-op port for execution. All other instructions are distributed to the proper execution pipes in a normal manner. Because the NOP instructions do not use the execution resources of other instructions, all instruction threads can be executed in one cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.