Interconnect structure for an integrated circuit and method of fabrication
US7151051B2 · kind B2 · utility
5Cited by
6References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2005 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | May 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.