Method for testing semiconductor devices and an apparatus therefor
US7151388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Sep 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing integrated circuit devices and loading such devices into a test board for further testing and an apparatus therefor is disclosed. The method allows for selection between two modes of operation. In a first mode, the integrated circuit devices are subjected to an electrical test before being placed into the test board for further testing. In a second mode, the integrated circuit devices are tested after being placed in the test board. The apparatus allows for the selection between the first mode and the second mode. In either mode, information about the tested devices and the sockets in the test board is used to load the test boards intelligently. Intelligent loading means that devices under test (DUTs) are not placed in bad sockets and devices that do test bad are removed from the test board, with an option of replacing the failed DUT with another DUT before subsequent environmental testing of the DUTs in the test board is carried out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.