Data converter with multiple conversions for padded-protocol interface
US7151470B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2004 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Jul 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data converter, or “gearbox,” for a padded protocol interface can perform a number of different conversions—e.g., between 64 and 66 bits, between 24 and 26 bits, or between 48 and 50 bits. This is accomplished by clocking the gearbox at different clock speeds, all derived from the same master clock (which may be recovered from the data in a receiver embodiment) using programmable dividers that allow the user to select the clock speed. When the conversion is not that one with the maximum width for which the gearbox is designed, unused bits are ignored. The converter can also find padding bits, for alignment purposes, in data of different widths, again ignoring unused bits when the data are not the widest for which the converter is designed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.