Integrated circuit memory with fast page mode verify
US7151694B2 · kind B2 · utility
24Cited by
12References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2005 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Jul 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating an integrated circuit memory device includes applying a verify procedure in which the page of data and one or more bits from a set of replacement cells are matched with a pattern in parallel to indicate a verify result, where the page of data is “unrepaired” and may include one or more bits from defective bit lines. While matching to indicate a verify result, the one or more bits from defective bit lines in the page are masked. Flash memory and other memory devices implement the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.