Package substrate for integrated circuit and method of making the substrate
US7152313B2 · kind B2 · utility
1Cited by
9References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Oct 5, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T156/1309
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments, an article of manufacture includes a metal layer and a first dielectric layer in contact with a first face of the metal layer. The article of manufacture also includes a second dielectric layer in contact with a second face of the metal layer. The second face of the metal layer is opposite to the first face of the metal layer. The metal layer may be a continuous sheet having slots formed therein to allow the first and second dielectric layers to adhere to each other by way of the slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.