Method of forming self-aligned poly for embedded flash
US7153744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2004 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Apr 12, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.