Encapsulation method for SBGA
US7154185B2 · kind B2 · utility
4Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2003 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Mar 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for encapsulating an integrated circuit chip is described. An intergrated circuit chip is attached to a substrate; a stress buffering material only covers corners of the integrated circuit chip; and an encapsulation material coats the integated circuit chip and a portion of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.