Semiconductor memory storage device and its control method
US7154807B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 22, 2005 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Feb 22, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy judge circuit (3) includes a redundancy judge circuit address+1 controller (30), an even-numbered redundant address judge section (31), an odd-numbered redundancy judge section (32), a redundant address ROM (33), a redundant IOROM (34), and a select section (35). The redundancy judge circuit (3) may also include a memory cell circuit (2), a read circuit (4), and an address generator circuit (5). With this structure, redundancy remedy can be conducted even during the burst operation due to the 2-bit prefetch, and slowing of the read operation speed can be prevented. Because it is possible to reduce the signal bus length of a decode signal bus in a column direction to substantially half and to reduce a decode signal bus region to substantially half, it is possible to prevent the wiring density in the wiring region of the decode signal bus from becoming high thereby preventing an increase in the read speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.