Semiconductor memory device for simultaneously testing blocks of cells
US7154808B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2005 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | May 11, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a plurality of cell blocks, block controllers for activating or precharging word lines of each of the cell blocks according to an external active command and a precharge command, a sense amplifier for sensing a fine voltage shared by bit lines and complementary bit lines of the cell blocks, sense amplifier controllers for activating or precharging the sense amplifier according to the external active command and the precharge command, and outputting bit line isolation signals that control the connection between the sense amplifier and the cell block, a block address decoder for decoding external block addresses in normal mode to output a block select signal for selecting one cell block, and outputting a block select signal for selecting even or odd cell blocks according to one of the external block addresses in test mode, and a SES control block for outputting a bit line isolation control signal for controlling the bit line isolation signals and a sense amplifier enable signal according to a test mode signal, a bank active signal and a sense enable start signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.