Synchronous controlled, self-timed local SRAM block
US7154810B2 · kind B2 · utility
3Cited by
35References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2005 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Jan 31, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.