Reusable, built-in self-test methodology for computer systems
US7155370B2 · kind B2 · utility
17Cited by
25References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 20, 2003 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | May 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A methodology for testing a computer system using multiple test units, each test unit being associated with its respective core function circuitry. The core circuitry and its respective test unit are located in a primary integrated circuit component of the computer system, such as a processor, memory, or chipset. The on-chip test units communicate with one another and with other parts of the system, to determine whether a specification of the computer system is satisfied, without requiring a processor core of the computer system to execute an operating system program for the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.