Low power system and method for a data processing system
US7155618B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2002 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Nov 26, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are discussed to identify a recoverable state in a low power device. A low power device having an arbiter to grant system bus access to a plurality of bus masters is set to initiate a low power mode of operation. A low power controller within the low power device provides a request to the bus arbiter to initiate a low power mode. The bus arbiter stops granting bus requests to the bus masters and identifies when the system bus has processed all current bus accesses. When the system bus is idle, the bus arbiter returns a bus grant signal to the low power controller. Clocks associated with the bus masters are disabled to suspend the bus arbiters and allow less power to be consumed by the low power device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.