Method and apparatus for testing embedded memory on devices with multiple processor cores
US7155637B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2003 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Dec 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable. Similarly, if the testing process determines that the failures in the embedded memory array can be repaired, then a signal is provided directly to an external testing apparatus indicating that the embedded memory array is repairable. Lastly, if no failures are found in an embedded memory array, then a signal is provided to an external testing apparatus indicating that the embedded memory array contain…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.