Coaxial through chip connection
US7157372B1 · kind B1 · utility
98Cited by
6References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 10, 2006 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Jan 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S2301/176
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method performed on a wafer having multiple chips, each including a doped semiconductor and substrate, involves etching an annulus trench partially into the substrate, metalizing the annulus trench with a metal, etching a via trench within the periphery of the annulus trench, making a length of the via trench electrically conductive, and thinning the substrate to expose the metal and the electrically conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.