Method and apparatus for calibrating a delay line
US7157948B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2004 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Sep 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/085
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A reference counter is clocked by a reference clock and has a reference count. A control circuit controls the delay and reference counters, compares a representation of the delay count to a representation of the reference count and responsively generates a modified value for the delay setting to reduce a difference between the representations of delay count and the reference count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.