Network with programmable interconnect nodes adapted to large integrated circuits
US7159047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2004 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Mar 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.