Link layer device with configurable address pin allocation
US7159061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2003 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Sep 8, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for flexible allocation of address pins of an interface bus to particular sub-buses of the interface bus. The interface bus is between at least one physical layer device and a link layer device in a communication system. Each of the sub-buses has an interface block of the link layer device associated therewith, the interface bus being configurable to carry a composite address signal having a plurality of portions each associated with one of the address pins of the interface bus. The interface blocks of the link layer device are controlled such that each of at least a subset of the interface blocks utilizes only particular ones of the address pins that are controllably allocated to the associated sub-bus in accordance with configuration information stored in the link layer device. The composite address signal is generated as a combination of address outputs of the interface blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.