Direct processor cache access within a system having a coherent multi-processor protocol
US7159077B2 · kind B2 · utility
10Cited by
0References
30Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Jun 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system has a plurality of processors in a multiprocessor system with each processor associated with a cache memory. The cache traffic is monitored by the respective processors to determine the load for each of the cache memories. Signals corresponding to the cache loads are generated and analyzed. A target processor is selected for a push data operation from a bus agent to the cache memory using the load information. The push operations to the caches are optimized based on the cache traffic information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.