System and method to trace high performance multi-issue processors
US7159101B1 · kind B1 · utility
9Cited by
91References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 28, 2003 |
| Grant date | Jan 2, 2007 |
| Priority date | — |
| Expiry date | Sep 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for program counter and data tracing in a multi-issue processor is disclosed. Instructions are traced in program sequence order. In one embodiment instructions are traced in graduation order from a reorder buffer. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.