Define via in dual damascene process
US7160799B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2003 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jan 13, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention includes a process for manufacturing an integrated circuit, comprising providing a substrate comprising a dielectric layer over a conductive material, depositing a hardmask over the dielectric layer, applying a first photoresist over the hardmask and photodefining a trench, etching the hard mask and partially etching the dielectric to form a trench having a bottom, stripping the photoresist, applying a second photoresist and photodefining a slit across the trench, selectively etching the dielectric from the bottom of the trench down to the underlying conductive material. Both the hardmask and the second photoresist are used as a mask. Later, a connection to the underlying metal is formed and integrated circuits made thereby.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.