Method of fabricating MOS transistor by millisecond anneal
US7160804B2 · kind B2 · utility
1Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2005 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Aug 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.