Memory bus within a coherent multi-processing system having a main portion and a coherent multi-processing portion
US7162590B2 · kind B2 · utility
37Cited by
2References
18Claims
0Family size
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Key dates
| Filing date | Mar 1, 2004 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jan 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Within a coherent multi-processing system multiple processor cores 4, 6 are coupled via respective memory buses to a memory access control unit 16. The memory buses are formed of a uni-processing portion containing signals specifying a memory access request in accordance with a uni-processing protocol. This uni-processing bus is augmented by a multi-processing bus containing signals giving additional information concerning memory access requests which may be used by the memory access control unit to service those requests and manage coherency within the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.