Stuart David Biles
53Patents
12h-index
58Co-inventors
87Inventor score
Filing activity: Oct 8, 1996 → Apr 19, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7937535B2 | Managing cache coherency in a data processing apparatus | Emerging Cross-Sectional Technologies | 427 | Active |
| US7657694B2 | Handling access requests in a data processing apparatus | Physics | 263 | Active |
| US8099556B2 | Cache miss detection in a data processing apparatus | Physics | 42 | Active |
| US7162590B2 | Memory bus within a coherent multi-processing system having a main portion and a coherent multi-processing portion | Physics | 37 | Expired |
| US8271730B2 | Handling of write access requests to shared memory in a data processing apparatus | Physics | 32 | Active |
| US7707390B2 | Instruction issue control within a multi-threaded in-order superscalar processor | Physics | 28 | Active |
| US5881263A | Non-instruction base register addressing in a data processing apparatus | Physics | 24 | Expired |
| US7886098B2 | Memory access security management | Physics | 17 | Active |
| US8041897B2 | Cache management within a data processing apparatus | Physics | 15 | Active |
| US7805595B2 | Data processing apparatus and method for updating prediction data based on an operation's priority level | Physics | 12 | Active |
| US7831817B2 | Two-level branch prediction apparatus | Physics | 12 | Active |
| US7769955B2 | Multiple thread instruction fetch from different cache levels | Physics | 12 | Active |
| US7343482B2 | Program subgraph identification | Physics | 12 | Expired |
| US8205206B2 | Data processing apparatus and method for managing multiple program threads executed by processing circuitry | Physics | 11 | Active |
| US7966466B2 | Memory domain based security control with data processing systems | Physics | 11 | Active |
| US8055872B2 | Data processor with hardware accelerator, accelerator interface and shared memory management unit | Physics | 10 | Active |
| US7743238B2 | Accessing items of architectural state from a register cache in a data processing apparatus when performing branch prediction operations for an indirect branch instruction | Physics | 10 | Expired |
| US7865675B2 | Controlling cleaning of data values within a hardware accelerator | Physics | 10 | Active |
| US9513959B2 | Contention management for a hardware transactional memory | Physics | 9 | Active |
| US7269759B2 | Data processing apparatus and method for handling corrupted data values | Physics | 9 | Expired |
| US7529889B2 | Data processing apparatus and method for performing a cache lookup in an energy efficient manner | Emerging Cross-Sectional Technologies | 7 | Active |
| US8195886B2 | Data processing apparatus and method for implementing a replacement scheme for entries of a storage unit | Physics | 6 | Active |
| US7506091B2 | Interrupt controller utilising programmable priority values | Physics | 6 | Active |
| US7350055B2 | Tightly coupled accelerator | Physics | 6 | Expired |
| US8725953B2 | Local cache power control within a multiprocessor system | Emerging Cross-Sectional Technologies | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.