Multilevel signal interface testing with binary test apparatus by emulation of multilevel signals
US7162672B2 · kind B2 · utility
14Cited by
20References
26Claims
0Family size
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Key dates
| Filing date | Sep 14, 2001 |
| Grant date | Jan 9, 2007 |
| Priority date | — |
| Expiry date | Jul 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Error detection mechanisms for devices that have multilevel signal interfaces test multilevel signals of an interface with a binary test apparatus. The error detection mechanisms include converting between multilevel signals of the interface and binary signals of the test apparatus. The error detection mechanisms also include repeated transmission of multilevel signals stored in a memory of a device having a multilevel signal interface for detection by the test apparatus at different binary levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.