Flip chip package and manufacturing method thereof
US7163840B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2004 |
| Grant date | Jan 16, 2007 |
| Priority date | — |
| Expiry date | Dec 29, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.